FEC Document {_id}


Generated: {timestamp_generated}

ECAL Time: {timestamp_ecal}

Metadata

Approval
{?approved}Approved{:else}Not approved{/approved}
Edited
{?edited_date}Yes ({edited_date}){:else}No{/edited_date}
ECAL
{ecal_id}
Comments
    {#comment}
  • {.}
  • {/comment}

Configuration

Crate: {crate}
Slot: {card}
FEC: {board_id}
PMTIC: {id.hv}
Daughterboards
Relays: {#relay_on}{?.}ON{:else}OFF{/.} {/relay_on}

Problems

{#channel_ids}{/channel_ids} {#channel.problem}{/channel.problem} {#tube.problem}{/tube.problem}
{.}
Channel{.}
PMT{.}

Hardware Settings

Vint DAC {hw.vint}
HVref DAC {hw.hvref}
NHIT100 Trigger {#channel_ids}{/channel_ids} {#hw.tr100.mask}{/hw.tr100.mask} {#hw.tr100.delay}{/hw.tr100.delay}
Channel{.}
Mask{.}
Delay{.}
NHIT20 Trigger {#channel_ids}{/channel_ids} {#hw.tr20.mask}{/hw.tr20.mask} {#hw.tr20.delay}{/hw.tr20.delay} {#hw.tr20.width}{/hw.tr20.width}
Channel{.}
Mask{.}
Delay{.}
Width{.}
SCMOS {#channel_ids}{/channel_ids} {#hw.scmos}{/hw.scmos}
Channel{.}
Value{.}
VBAL {#channel_ids}{/channel_ids} {#vballo}{/vballo} {#vbalhi}{/vbalhi}
Channel{.}
Low{.}
High{.}
Tdisc {#chip_ids}{/chip_ids} {#hw.tdisc.rmpup}{/hw.tdisc.rmpup} {#hw.tdisc.vsi}{/hw.tdisc.vsi} {#hw.tdisc.vli}{/hw.tdisc.vli} {#hw.tdisc.rmp}{/hw.tdisc.rmp}
Chip{.}
RMPUP{.}
VSI{.}
VLI{.}
RMP{.}
TCMOS
Vmax {hw.tcmos.vmax}
VTACref {hw.tcmos.vtacref}
Iseta {#hw.tcmos.iseta}{.} {/hw.tcmos.iseta}
Isetm {#hw.tcmos.isetm}{.} {/hw.tcmos.isetm}
TAC trim {#channel_ids}{/channel_ids} {#hw.tcmos.tac_trim}{/hw.tcmos.tac_trim}
{.}
{.}
VTHR zero {#channel_ids}{/channel_ids} {#hw.vthr_zero}{/hw.vthr_zero}
Channel{.}
Value{.}
VTHR threshold {#channel_ids}{/channel_ids} {#vthrs}{/vthrs}
Channel{.}Override checks
Value

Tests