Java tutorial
/** * Copyright (c) 2013 Martin Geisse * * This file is distributed under the terms of the MIT license. */ package name.martingeisse.esdk.model.hdl.assembler.verilog; import java.util.HashSet; import java.util.Set; import org.apache.commons.collections.Bag; import org.apache.commons.collections.bag.HashBag; import name.martingeisse.esdk.model.hdl.core.BitSignal; import name.martingeisse.esdk.model.hdl.core.Register; import name.martingeisse.esdk.model.hdl.core.Signal; import name.martingeisse.esdk.model.hdl.module.port.InputPort; import name.martingeisse.esdk.model.hdl.util.RegisterBlockedRecursiveCommonHandlerSignalVisitor; /** * This visitor checks which signals require top-level declaration. * This does not include registers. */ public class SignalDeclarationRequirementDetector extends RegisterBlockedRecursiveCommonHandlerSignalVisitor { /** * the result */ private final Set<Signal> result; /** * the bag */ private final Bag bag; /** * Constructor. */ public SignalDeclarationRequirementDetector() { this.result = new HashSet<>(); this.bag = new HashBag(); } /* (non-Javadoc) * @see name.martingeisse.esdk.model.hdl.util.RecursiveCommonHandlerSignalVisitor#handleSignal(name.martingeisse.esdk.model.hdl.core.Signal) */ @Override protected void handleSignal(final Signal signal) { // always declare the clock signal for registers, unless they are self-declaring if (signal instanceof Register<?, ?>) { final BitSignal clock = ((Register<?, ?>) signal).getClock(); if (!isSelfDeclaring(clock)) { result.add(clock); } return; } // all non-self-declaring signals must be declared if used more than once if (!isSelfDeclaring(signal)) { if (!bag.add(signal)) { result.add(signal); } } } private boolean isSelfDeclaring(final Signal signal) { return ((signal instanceof InputPort<?>) || (signal instanceof Register<?, ?>)); } /** * Getter method for the result. * @return the result */ public Set<Signal> getResult() { return result; } }